The Silicon Photonics Integrated Circuit in the Optical I/O Core comprises Mach-Zehnder Interference (MZI) modulators, Germanium photodetectors, Spot Size Converters (SSC) for Laser Diode (LD) coupling and Vertical Grating Couplers.
The substrate includes a cavity and alignment markers allowing the source LD to be passively aligned and mounted into the chip.
Electrical contacts are provided on the optical integrated circuit including pads for flip-chip mounting the driver IC to the modulator, and electrical input/output terminals on the periphery.
The process uses a 300 mm SOI wafer.
High Temperature operation
In the MZI modulator, the expression for modulation efficiency is given by C × V (where C =Capacitance, V = supply voltage). As C is temperature independent and the modulation voltage is constant, the frequency band is stable over a wide temperature range. Therefore, a very stable optical output waveform with low jitter can be obtained over a wide temperature range.
A Quantum Dot Fabry-Perot laser is used as the light source. Quantum Dot lasers exhibit low temperature dependence in their L-I characteristics and can provide sufficient optical output even at very high temperatures. Also, it includes the feature that reflected return light noise is very small. Optical I/O Core can therefore be used over a wide temperature range. The light output waveform of the current product from -40 °C to 85 °C is shown.
When an Optical I/O Core is mounted around a logic LSI (e.g. a Co-Packaged Optical module) or used in a harsh environment, operation at 100 °C or higher may be required. We are developing an Optical I/O Core that operates at temperatures above 100 °C, and plan to release it in the near future.
The following images show an example of an optical output waveform at 100 °C.
The cost of an optical transceiver can be broadly divided into device and implementation. It is sometimes said that Si photonics is cheap, because it can be mass-produced by a process equivalent to CMOS, but this is not necessarily true. In the case of silicon photonic integrated circuits, cost is determined largely by the size of the chip. By reducing the size of the chip and increasing the yield, a lower cost is achieved.
In the Optical I/O Core micro-transceiver, the optical interface area is minimized by optimizing the mounting structure, and the chip area is reduced by mounting the IC and LD as bare die. The 100 Gbps micro-transceiver chip has a size of 5 mm x 5 mm, which makes it the smallest chip in the world with this function. As shown below, this size will be further reduced in the future.
Ar immersion technology is applied to 300 mm SOI wafers. The device is designed with robustness in mind. Therefore, the characteristics in the wafer are very uniform and chips can be obtained with a very high yield.
By producing smaller chips in higher yields than anywhere else, we have succeeded in significantly reducing the cost of our Si photonic chips.